NII Shonan Meeting No.133 - No.133 Asynchronous Circuit Design and Its Applications: Past, Present and Future

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Welcome to NII Shonan Meeting Seminar No.133. The official page for this meeting is here.

Bus schedule

Bus Time table (20190509) .pdf

Train schedule

The following trains are local trains (Yokosuka-line), but they start from JR Zushi station (it means it is easier to find empty seats), and directly take you up to Narita Airport without changes.
- 13:42 (Zushi) --(25 stations)-- 16:16 (NRT Terminal2) -- 16:18 (NRT Terminal 1) # Taxi needed (around 12:45)
- 15:38 (Zushi) --(25 stations)-- 18:07 (NRT Terminal2) -- 18:10 (NRT Terminal 1) # 14:45 bus is probably OK
- 16:46 (Zushi) --(25 stations)-- 19:20 (NRT Terminal2) -- 19:23 (NRT Terminal 1) # 15:45 bus is probably OK

The following trains are similar, but they start before JR Zushi station (it means it happens all seats are occupied when you get in).
- 15:12 (Zushi) --(25 stations)-- 17:40 (NRT Terminal2) -- 17:43 (NRT Terminal 1) # 13:45 bus is OK, but the waiting time is a bit long
- 16:09 (Zushi) --(25 stations)-- 18:38 (NRT Terminal2) -- 18:41 (NRT Terminal 1) # This may be a back-up for 15:38 train

Advantage

Often cited (1-10 @ ASYNC1994, +11-17 @ SHONAN133)
- 1. Achieve average Case Performance
- 2. Power consumed only when needed
- 3. Ease of modular composition
- 4. No clock alignment at the interfaces
- 5. Metastability has time to end
- 6. Avoid clock distribution costs
- 7. Easier to exploit concurrency
- 8. Intellectual challenge
- 9. Intrinsic elegance
- 10. Global synchrony does not exist anyway
- 11. Low EMI/noise
- 12. Process Bring-up support
- 13. Robust to PVT variations
- 14. Easier to interface to analog
- 15. Outlives CMOS
- 16. Intrinsically bio-inspired
- 17. Continuous time information processing

NOT often cited (1-10 @ ASYNC1994, +11-17 @ SHONAN133)
- 1. It really pisses my boss off
- 2. I like reinventing wheels
- 3. I like to be different
- 4. Gee - I really don’t know
- 5. People and circuits need to play by same rules
- 6. I don't understand synchronous circuits
- 7. World problems stem from glithces
- 8. Synchronous design gives me gas
- 9. Clock radiation causes hair loss
- 10. It’s none of your business
- 11. Clocks make me late
- 12. Asynchronous design makes me GasP
- 13. Forever the future technology
- 14. Timing is where the rubber hits the road
- 15. It confuses proposal reviewers
- 16. What else to call computing without clocks
- 17. I’m still waiting for an ack

Tentative plan to travel from ASYNC2019 to Shonan Meeting

5/15 (Wed) :

12:24 Hirosaki -> 13:03 Shin-Aomori (Local train) (or 12:57 Hirosaki -> 13:39 Shin-Aomori)

13:52 Shin-Aomori -> 17:04 Tokyo (Hayabusa 24, Shinkansen train: Sheet reservations will be arranged by the organizers)

17:26 Tokyo -> 18:30 Zushi (Local train)

18:35 Zushi -> 19:00 Hotel (Taxi or Local bus)

Organizers

Participant	Research Interests	Shonan Talk Title	Abstract
Tomohiro Yoneda	Asynchronous reconfigurable system design	Coarse grained vs. Fine grained architectures for asynchronous reconfigurable devices	yoneda.txt
Peter A. Beerel	Bundled-Data Design	Useful variations of Bundled-Data Design	beerel.txt
Alex Yakovlev	Asynchronous-Analog Co-design	Asynchronous control for Analog-Mixed Signal	yakovlev-abstract.txt
Masashi Imai	Hardware Trojan, Scalable Delay Insensitive Design	QDI and SDI Design in Subthreshold Region	imai.txt

Participants

Participant	Research Interests	Shonan Talk Title	Abstract
Snorre Aunet	ultra low power / low energy asynchronous circuits	asynchronous ultra low voltage / low power CMOS - what and why, but not much about how.
Ney Laert Vilar Calazans	QDI design templates and circuit design	QDI Circuits: Efficient Templates and Design Techniques	calazans.txt
Hong Chen	Dataflow circuits, Bundled-data design	Asynchronous Energy-Efficient CNN Accelerator Design with Reconfigurable Architecture
Huimei Cheng	Desynchronization, Latch-based design	Opportunity and challenge of latch-based designs	huimei.txt
Jordi Cortadella	Dataflow circuits, Synthesis of Asynchronous Controllers	High-Level Synthesis and Dataflow Circuits	cortadella.txt
Jia Di	Applications of QDI Circuits	Applications of QDI Circuits	Di.txt
Matthias Fuegger	timed designes, metastability, biological circuits, asynchronous & analog designs	Gradient clock generation
Mark Greenstreet	clock domain crossing, metastability, formal verification, timed design, analog design	Meditation on Metastability
Takahiro Hanyu	Design and fabrication of nonvolatile logic-in-memory circuits and their applications	Challenge of nonvolatile logic LSI for IoT applications	hanyu.txt
Yong Hei	Universal asynchronous model plus higher and lower level support	There is Enough for All - Part 3	Shonan2019_ARCabstract.txt
Warren A. Hunt, Jr	self-timed systems, formal logic, mechanical verification	Specification and Verification of Link-Joint-Style System Designs
William Koven	Industrial asynchronous design	Practical Mixed Asynchronous/Synchronous Design
Milos Krstic	low noise GALS & asynchronous circuits, fault tolerant asynchronous circuits, radhard design	Fault tolerant asynchronous design	krstic.txt
Andrew Lines	async circuits & CAD	CAST+CSP+Proteus
Rajit Manohar	design automation for async	teaching: from principles to tapeout in a semester	rajit.txt
Mika Nystroem
Naoya Onizawa	Stochastic computing	CMOS invertible logic using stochastic computing	onizawa.txt
Marly Roncken	Universal asynchronous model plus higher and lower level support	There is Enough for All - Part 2	Shonan2019_ARCabstract.txt
Hiroshi Saito	Design automation, Bundled-data design	A design support tool set for bundled-data implementation	saito.txt
Shogo Semba	Design automation, Bundled-data design	Conversion from synchronous RTL models to asynchronous ones	semba.txt
Montek Singh
Scott C. Smith	Low-Power, Rad-hard, & Extreme Environment QDI Design, Design Automation, Verification	Verification of QDI Circuits	SCSmith.txt
Jens Sparsoe	Designing asynchronous circuits. Networks-on-chip. Teaching.	Asyncchronous in mesochronous (Timing analysis). Teaching and Tools: where are we?	sparsoe-abstract.txt
Andreas Steininger	Fault-tolerant async design, QDI, DI coding, clock domain crossing, metastability	Fault modeling and fault masking in asynchronous circuits	steininger.txt
Ken Stevens	Timing, verification, and modeling	Breaking through the inertia: the force to move asynchronous design into the mainstream
Ivan Sutherland	Universal asynchronous model plus higher and lower level support	There is Enough for All - Part 1	Shonan2019_ARCabstract.txt
Nobuyuki Yoshikawa	Energy-efficient superconducting logic circuits	Synchronous and asynchronous LSI design for energy-efficient superconducting logic circuits	yoshikawa.txt
Daniel Zimmerman	correct-by-construction high-level synthesis

Final Program (updated on May 15)

5/15 (Wed)
- 18:00-19:30 Registration
- 19:30-21:00 Welcome Reception

5/16 (Thu) @ Research Wing 208
- 9:00-10:00 Opening, Introduction by everybody (1 min. per person)
- 10:00-11:00 6 Talks (10min. per person)
  - Ivan
  - Marly
  - Yong
  - Peter
  - Hiroshi
  - Shogo
- 11:00-11:15 (Break)
- 11:15-12:15 6 Talks (10min. per person)
  - Jordi
  - Masashi
  - Ney
  - Scott
  - Andreas
  - Montek
- 12:15-14:00 (Lunch)
- 14:00-14:20 Photo Session (Meet at the front desk)
- 14:20-15:20 6 Talks (10min. per person)
  - Mika
  - Jens
  - Snorre
  - Jia
  - Huimei
  - Rajit
- 15:30-15:45 (Break)
- 15:45-16:45 6 Talks (10min. per person)
  - Andrew
  - Alex
  - Warren
  - Milos
  - Matthias
  - Hong
- 17:00-17:15 (Break)
- 17:15-18:25 7 Talks (10min. per person)
  - Ken
  - Tomohiro
  - Daniel
  - William
  - Mark
  - Takahiro
  - Naoya
- 18:45-19:45 (Dinner)
- 19:45- Discussions for tomorrow's panels with drinks (@ Research Wing 208)
  - Peter (Chair)

5/17 (Fri)
- 09:00-10:10 Panel 1: Open source
  - Alex (chair)
  - Panelists
    - Andrew
    - Rajit
- 10:10-10:15 (Break)
- 10:15-11:10 Panel 2: Community involvement
  - Montek (chair)
  - Panelists
    - All
- 11:10-11:20 (Break)
- 11:20-12:00 Panel 3: Next day planning
  - Peter (chair)
- 12:00-13:30 (Lunch)
- 13:30-20:45 Excursion (Dinner is included)
  - (The detailed schedule is shown in Kamakura Sightseeing Tour (Kotokuin-Hase).pdf)

5/18 (Sat)
- 09:00-11:00 Panel 4: Education
  - Mika (chair)
  - Panelists
    - Peter
    - Rajit
    - Montek
    - Jens
- 11:00-11:15 (Break)
- 11:15-12:10 Panel 5: IP & library developer
  - Scott (chair)
  - Panelists
    - William
    - Jia
    - Ney
    - Jordi
- 12:10-13:30 (Lunch)
- 13:30-14:15 Panel 5: IP & library developer (continued)
  - Scott (chair)
  - Panelists
    - William
    - Jia
    - Ney
    - Jordi
- 14:15-15:15 Panel 6: User application
  - Ken (chair)
  - Panelists
    - Milos
    - Hong
- 15:15-15:45 (Break)
- 15:45-16:30 Panel 7: Next day planning
  - Peter (chair)
- 18:00- (Dinner and Discussion in Lounge)

5/19 (Sun)
- 09:00-11:00 Panel 8: Tangible Next Steps
  - Peter (chair)
- 11:00-11:10 (Break)
- 11:10-11:30 Wrap-up and closing
- 11:30-13:00 (Lunch and Departure)

Advance Program (updated on May 11)

5/15 (Wed)
- 18:00-19:30 Registration
- 19:30-21:00 Welcome Reception

5/16 (Thu)
- 9:00-10:00 Opening, Introduction by everybody (1 min. per person)
- 10:00-11:00 3 Talks (20min. per person)
  - Ivan
  - Marly
  - Yong
- 11:00-11:15 (Break)
- 11:15-12:35 4 Talks (20min. per person)
  - Peter
  - Hiroshi
  - Shogo
  - Jordi
- 12:35-14:40 (Lunch)
- 14:40-15:25 Panel 1: Bundled-Data Design: Opportunities & Challenges (Moderator: Peter Beerel)
  - Panelists
    - Jordi
    - Marly
    - Hiroshi
    - Peter
- 15:25-15:40 (Break)
- 15:40-17:00 4 Talks (20min. per person)
  - Masashi
  - Ney
  - Scott
  - Andreas
- 17:00-17:15 (Break)
- 17:15-18:00 Panel 2: Dual-Rail Design: Opportunities & Challenges (Moderator: Masashi Imai)
  - Panelists
    - Andreas
    - Andrew
    - Ney
    - Scott
    - Masashi
- 18:00- (Dinner and Discussion in Lounge)

5/17 (Fri)
- 9:00-10:00 3 Talks (20min. per person)
  - Montek
  - Mika
  - Jens
- 10:00-10:45 Panel 3: Teaching Async (Moderator: Mika Nystrom)
  - Panelists
    - Jens
    - Rajit
    - Mika
- 10:45-11:00 (Break)
- 11:00-12:00 3 Talks (20min. per person)
  - Snorre
  - Jia
  - Huimei
- 12:00-13:30 (Lunch)
- 13:30-20:45 Excursion (Dinner is included)
  - (The detailed schedule is shown in Kamakura Sightseeing Tour (Kotokuin-Hase).pdf)

5/18 (Sat)
- 9:00-10:00 3 Talks (20min. per person)
  - Rajit
  - Andrew
  - Alex
- 10:00-10:45 Panel 4: Open-Source Tools - Where are we? (Moderator: Alex Yakoviev)
  - Panelists
    - Peter
    - Rajit
    - Andrew
    - Alex
- 10:45-11:00 (Break)
- 11:00-12:20 4 Talks (20min. per person)
  - Warren
  - Takahiro
  - Naoya
  - Milos
- 12:20-14:45 (Lunch)
- 14:45-15:45 3 Talks (20min. per person)
  - Ken
  - Matthias
  - Nobuyuki
- 15:45-16:00 (Break)
- 16:00-16:40 2 Talks (20min. per person)
  - Hong
  - Tomohiro
- 16:40-17:25 Panel 5: The Future of Async Design (Moderator: Tomohiro Yoneda)
  - Panelists
    - Ken
    - Matthias
    - Nobuyuki
    - Hong
- 18:00- (Dinner and Discussion in Lounge)

5/19 (Sun)
- 9:00- 10:00 3 Talks (20min. per person)
  - Daniel
  - William
  - Mark
- 10:00-10:15 (Break)
- 10:15-11:30 Wrap-up and Closing
- 11:30-13:00 (Lunch and Departure)

Expenses

The following rates cover overnight accommodation (single room) and full board (breakfast, lunch, and dinner) per day:
- Participants from academia: 8,000 Yen/day
- Participants from industry: 15,000 Yen/day

You will be asked to pay the above expenses by your credit cards about 6 weeks before the meeting.

NOTE: In the above expenses, excursion fees are not included. We will ask you additional fee for excursion.

Hotel Reservation

The hotel rooms for the Shonan Meeting (4 nights from 5/15) have already been booked, and so, you don't have to worry about them.
If you would like to stay at the hotel before or after the meeting, please contact the Shonan meeting office (shonan [at] nii.ac.jp).

Last modified:2019/05/21 12:48:52
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No.133 Asynchronous Circuit Design and Its Applications: Past, Present and Future