Given that the venue is a workshop, I would like to bring up some open issues that I am struggling with. The first issue is CAD tools. I have followed the field for 30 years and have seen tools come and go. When I teach asynchronous design to graduate students I can't really point them to tools except perhaps Petrify/WorkCraft for synthesizing speed independent controllers, should they need such control circuits in their design. Could our workshop produce an updated list of what CAD tools are available? What tools could/should I use in the next edition of my class on asynchronous circuit design. The second issue is timing-analysis. At DTU, we have developed an asynchronous time-division-multiplexed network-on-chip (called Argo) that we use in our real-time multi-core platform (called T-CREST). The timing organization of this multi-core processor allow: (a) individually clocked processors, (b) mesochronously clocked network interfaces, and (c) connected by an asynchronous network of routers and links. In every clock cycle, every network interface reads one token from the asynchronous network and writes one token into the asynchronous network. Tokens can carry valid data or voids, and in this way the circuit mimics a global-clock. The operation is similar to Mark Greenstreet's STARI, generalized to a structure with multiple input and output ports. The advantage is that the design offers time elasticity without any synchronizers. We believe the scheme can be used in many other contexts. The correct and safe operation requires that the interfaces to the asynchronous network are able to complete a handshake cycle in less time than the duration of a clock period. This timing analysis problem was addressed by Hulgaard et al. in the 1990s and more recently in 2018 by Hua and Manohar. Questions: Are the timing models of the circuit realistic? Is it enough to focus on the steady-state operation. Are the developed algorithms implemented in tools? Etc.